1. Field of the Invention
The present invention relates to a method and apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices.
2. Discussion of the Related Art
As is known in integrated circuit technology it is often necessary to electrically insulate some regions of the chip from others. For example, in a VIP circuit the driving circuit must be insulated from the power transistor.
One technique used for insulation is junction insulation. However, this technique unavoidably forms parasitic transistors which ultimately define the actual operating limits of the entire structure of the integrated circuit.
FIG. 1 illustrates a typical structure of a MOSFET power transistor circuit. The MOSFET structure typically comprises a substrate 1, doped with impurities of the N.sup.+ type, which acts as a drain terminal of the MOSFET device. An epitaxial layer 2 of the N.sup.- type is grown on the substrate 1. Two regions 3a and 3b of the P.sup.+ type, known as deep-body regions, are located in the epitaxial layer. Above the respective deep-body regions 3a and 3b there are body regions 4a and 4b which are doped with P-type impurities. Two source regions, respectively 5a and 5b for the body region 4a, and 5d and 5c for the body region 4b, are accommodated in each one of the body regions 4a and 4b.
An oxide layer 10a is located above the adjacent edges of the body regions 4a and 4b, and the polysilicon gate 6a is placed on layer 10a. The gate 6a is covered by a dielectric layer 7a, which is preferably a chemical vapour deposited oxide, such as P-Vapox. Gate terminals 6b and 6c, having related oxides 10b and 10c and dielectric layers 7b and 7c, are located at the edges of the body regions 4a and 4b.
Finally, the entire structure is covered with a layer of metal, preferably aluminum, which makes contact with the body regions 4a and 4b and with the source regions 5a, 5b, 5c, and 5d.
This structure includes parasitic transistors which limit its operation. The emitters, bases and collectors of these parasitic transistors are respectively the sources 5a-d, the deep-body regions 3a and 3b or body regions 4a and 4b, and the drain, which is constituted by the substrate 1. The emitters, bases and collectors of the parasitic transistor comprise their active regions. One of these parasitic transistors is shown in FIG. 1 and is designated by the reference numeral 9. The emitter of the transistor 9 is constituted by the source region 5d, the base is constituted by the body/deep-body region 3b, and the collector is constituted by the substrate 1. It is evident that there are at least three other parasitic transistors which are present with the source/deep-body/drain combinations. They have not been illustrated for the sake of simplicity.
The following three methods may be used to reduce the gain of the parasitic transistor 9. First, the deep-body region 3b, i.e. the base of the transistor, may be doped heavily. Secondly, the source 5d and the deep body 3b or the body 4b, i.e. the emitter and the base of the transistor 9, are shorted. Third, the source 5d may be manufactured as short as possible, within the limits of the photolithographic technology available.
Despite these methods, when the PMOS is on there is a voltage drop in the deep-body portion underlying the source. A positive bias V.sub.be can thus be formed between the base and the emitter of the transistor 9, turning the transistor on. The gain of this parasitic transistor increases as current and temperature increase, limiting the performance of the PMOS.
FIG. 2 illustrates a typical structure of an IGBT device. The structure of the IGBT is similar to the structure of the PMOS device of FIG. 1, except that there is an additional epitaxial layer 2a which is interposed between the epitaxial layer 2 and the substrate 1 and is doped with impurities of the N.sup.+ type.
The IGBT device includes an NPN-type parasitic transistor 10 of FIGS. 2 and 5 the collector, base, and emitter of which are formed respectively by the source region 5d, the body/deep-body region 4b/3b, and the epitaxial layer 2 or 2a. The effect of the transistor 10 combines with the effect of another parasitic transistor 11 of the PNP type, the collector, base, and emitter of which are respectively the body/deep-body 4b/3b, the epitaxial layer 2 or 2a, and the substrate 1. Of course other parasitic transistors can form in the other body/deep-body region.
The two parasitic transistors 10 and 11 constitute a thyristor. In order to avoid activating this thyristor it is necessary to reduce the gain of the two transistors so that .sup..alpha. NPN.sup.+.alpha. PNP.sup.&lt;1.
Two techniques are used to reduce the gain of the PNP transistor 11. The first technique is the introduction of a buffer layer between the P-type substrate 1 and the N-type drain. This layer is heavily doped with N-type impurities. The second technique is to implant a lifetime killer metal, such as gold or platinum, which is then diffused to distribute it uniformly throughout the thickness of the wafer. The gain of the NPN transistor 10 is of course also reduced by this.
The operating conditions for which the above described parasitic components are particularly detrimental are, in the case of the PMOS (FIG. 1), dynamic dV/dt and unclamped conditions. In the case of the IGBT device (FIG. 2), static and dynamic latch-up are possible.
A third example of a power device in which parasitic transistors reside is a Vertical Intelligent Power device, better known as a VIP device. FIG. 3 illustrates a typical structure of a VIP device,
The VIP device comprises an N.sup.+ -type substrate 31 above which there is an N-type epitaxial layer 32. The epitaxial layer 32 accommodates the P.sup.+ -type buried layer 33. The P.sup.+ -type buried layer 33 accommodates the low-power control devices, typically a vertical NPN transistor 51 and a lateral PNP transistor 52. The P.sup.+ buried layer also acts as insulation for the low-power devices. The vertical NPN transistor 51 comprises a first N.sup.+ -type buried layer 34 which is connected to a collector terminal 35 by means of a sinker region 36 which is also doped with N.sup.+ -type impurities. The N.sup.+ buried layer 34 and the N.sup.- type region 41 that accommodates the P.sup.+ -type base 37 and the N.sup.+ -type emitter 38 of the NPN transistor are surrounded by two P.sup.+ -type insulation regions 39 and 40. These insulation regions form, together with the P.sup.+ buried layer 33, an insulation well of the N region 41.
Next to the vertical NPN transistor 51 is a lateral PNP transistor 52. This transistor also includes an N.sup.+ buried layer 42 which is connected to the base terminal 43 by means of a sinker region 44. The N.sup.- type region 45 accommodates the emitter 46 and the collector 47, both of which are of the P type, and is insulated by the insulation region 40 and an additional insulation region 48. The insulation regions 39, 40 and 48, together with the P.sup.+ buried layer, form a region that is termed the P-well.
The power device 53 comprises a base region 49, which is connected to the base terminal 50, and an emitter region 54, which is connected to an emitter terminal 55. The collector of the power device 53 is constituted by a metallic layer 30 which is connected to the substrate of the entire VIP device.
In the above described VIP structure, the low-power circuit (NPN transistor 51 and PNP transistor 52) must be insulated from the power transistor 53. The technique commonly used is junction insulation. However, this technique, as mentioned, unavoidably leads to the formation of parasitic transistors that limit the operation of the device.
The first example of a parasitic transistor is the transistor 61, having its emitter constituted by the base 37 of the NPN transistor 51, its base is constituted by the collector 35 of the NPN transistor 51, and its collector constituted by the P.sup.+ region or buried layer (P-well) 39.
The second parasitic transistor is the transistor 62, having its emitter constituted by the base 43 of the PNP transistor 52, Its base constituted by the region 40 of the P-well, and its collector constituted by the collector 35 of the NPN transistor 51.
The third parasitic transistor is the transistor 63, having its emitter constituted by the emitter 46 of the PNP transistor 52, its base constituted by the base 43 of the PNP transistor 52, and its collector constituted by the region 48 of the P-well.
The fourth parasitic transistor is the transistor 64 (which is superimposed on the transistor 63 in the FIG.), which is identical to the transistor 63, except that its emitter is constituted by the collector 47 of the PNP transistor 52.
The fifth parasitic transistor is the transistor 65, having its emitter constituted by the base 43 of the PNP transistor 52, its base constituted by the region 48 of the P-well, and its collector constituted by the epitaxial layer 32.
The sixth parasitic transistor is the transistor 66, having its emitter constituted by the base 49 of the power device 53, its base constituted by the epitaxial layer 32, and its collector constituted by the region 48 of the P-well.
It is evident that there are several parasitic transistors, each of which imposes limitations on the operating versatility of the structure.
As mentioned above, in order to obviate these parasitic components, there are various solutions, including the implantion or deposition of a metal (gold and platinum), and the subsequent diffusion and irradiation with nuclear particles (neutrons, protons and alpha), electrons or X-rays. The drawback of metal implanting is the complication of the processing flow-chart, whereas the drawbacks of irradiation are its high cost and the fact that it is difficult to control, since the thermal assembly steps reduce the effect of irradiation by a certain amount.
It should be stressed that in power devices there are not only parasitic transistors but also parasitic diodes. Furthermore, in addition to the three above described parasitic devices there are also others, such as fast-recovery diodes, transistors for small signals, thyristors, etc.